Hm-6514

1024 x 4 CMOS RAM
Features
Description
• Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max
The HM-6514 is a 1024 x 4 static CMOS RAM fabricatedusing self-aligned silicon gate technology. The device utilizes • Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
synchronous circuitry to achieve high performance and low • Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
On-chip latches are provided for addresses allowing efficientinterfacing with microprocessor systems. The data output • Common Data Input/Output
can be forced to a high impedance state for use in expanded • Three-State Output
• Standard JEDEC Pinout
Gated inputs allow lower operating current and also elimi-nate the need for pull up or pull down resistors. The • Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
HM-6514 is a fully static RAM and may be maintained in any • 18 Pin Package for High Density
state for an indefinite period of time.
• On-Chip Address Register
Data retention supply voltage and supply current are guaran-teed over temperature.
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
Ordering Information
TEMPERATURE RANGE
HM-6514 (PDIP, CERDIP)
HM-6514 (CLCC)
DESCRIPTION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 19996-1 Functional Diagram
REGISTER
REGISTER
I/O SELECT
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V CERDIP Package . . . . . . . . . . . . . . . .
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 PDIP Package . . . . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . .
Operating Conditions
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oCMaximum Junction Temperature Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC HM-6514S-9, HM-6514B-9, HM-6514-9 . . . . . . . . -40oC to +85oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC HM-6514B-8, HM-6514-8 . . . . . . . . . . . . . . . . . . -55oC to +125oC Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationof the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6514S-9, HM-6514B-9, HM-6514-9)
TA = -55oC to +125oC (HM-6514B-8, HM-6514-8) PARAMETER
TEST CONDITIONS
Capacitance TA = +25oC
PARAMETER
TEST CONDITIONS
f = 1MHz, All measurements arereferenced to device GND 1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
AC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6514S-9, HM-6514B-9, HM-6514-9)
TA = -55oC to +125oC (HM-6514B-8, HM-6514-8) HM-6514S-9
HM-6514B-9
HM-6514-9
PARAMETER
CONDITIONS
1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. VCC = 4.5V and 5.5V.
4. TAVQV = TELQV + TAVEL.
Timing Waveforms
(2) TAVQV
(17) TELEL
(7) TAVEL
VALID ADD
(2) TAVQY
(5) TELEH
(1) TELQV
(4) TEHQZ
(3) TELQX
VALID DATA OUT
REFERENCE
FIGURE 1. READ CYCLE
TRUTH TABLE
REFERENCE
FUNCTION
Cycle Ends, Next Cycle Begins (Same as 0) The address information is latched in the on-chip registers enabled, but data is not valid until during time (T = 2). W on the falling edge of E (T = 0). Minimum address set up and must remain high throughout the read cycle. After the output hold time requirements must be met. After the required hold data has been read, E may return high (T = 3). This will dis- time, the addresses may change state without affecting able the output buffer and all inputs, and ready the RAM for device operation. During time (T = 1) the output becomes Timing Waveforms (Continued)
VALID ADD
VALID DATA INPUT
REFERENCE
FIGURE 2. WRITE CYCLE
TRUTH TABLE
REFERENCE
FUNCTION
Cycle Ends, Next Cycle Begins (Same as 0) The write cycle is initiated by the falling edge of E (T = 0), This E and W control timing will guarantee that the data out- which latches the address information in the on-chip regis- puts will stay disabled throughout the cycle, thus, simplifying ters. There are two basic types of write cycles, which differ in the data input timing. TWLEL and TEHWH must be met, but the control of the common data-in/data-out bus.
TWLDV becomes meaningless and can be ignored. In thiscycle TDVWH and TWHDX become TDVEH and TEHDX. In other words, reference data setup and hold times to the E The output buffers may become enabled (reading) if E falls before W falls. W is used to disable (three-state) the outputsso input data can be applied. TWLDV must be met to allow the W signal time to disable the outputs before applying input data. Also, at the end of the cycle the outputs maybecome active if W rises before E. The RAM outputs and all inputs will three-state after E rises (TEHQZ). In this type of write cycle TWLEL and TEHWH may be ignored.
If a series of consecutive write cycles are to be performed, Case 2: E falls equal to or after W falls, and E rises before W may be held low until all desired locations have been writ- Test Load Circuit
(NOTE 1) CL
EQUIVALENT CIRCUIT
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